The stress memorization technique (SMT) and the stressed contact etching stop layer technique (stressed-CESL) are adopted to promote carrier mobility of a transistor. Through these two techniques, a stable stress can be formed in a channel region of a transistor, which promotes carrier mobility in the channel. A direction of the stress is parallel to a length direction of the channel and the stress may be a tensile stress or a compressive stress. Generally, the tensile stress makes atoms arranged sparsely in the channel so that mobility of electrons is promoted. The tensile stress is more suitable for NMOS transistors. In contrast, the compressive stress makes atoms arranged closely in the channel so that mobility of holes is promoted. The compressive stress is more suitable for PMOS transistors.
FIG. 1 to FIG. 3 are schematic cross-sectional views of intermediate structures illustrating a method for manufacturing a transistor having a tensile stress, as known in the prior art.
Referring to FIG. 1, a substrate 10 is provided on which a NMOS transistor and a PMOS transistor are formed. An insulating structure 11 is formed between the NMOS transistor and the PMOS transistor. The NMOS transistor includes a P trap (not shown), an NMOS transistor source/drain region 12 formed in the P trap and a NMOS transistor gate structure which is located between the NMOS transistor source/drain regions 12. The gate structure includes a gate oxide layer 17 disposed on the substrate, a gate 13 disposed on gate oxide layer 17 and spacers surrounding gate oxide layer 17 and overlying sidewalls of gate 13. The PMOS transistor includes an N trap, a PMOS transistor source/drain region 14 formed in the N trap and a PMOS transistor gate structure 15.
Referring to FIG. 2, a stressed layer 16 is formed on the NMOS transistor and the PMOS transistor to cover the source/drain regions 12, 14, the gate structures and the substrate 10. The stressed layer includes silicon nitride and provides a tensile stress or a compressive stress. If the stressed layer 16 provides a tensile stress, the performance of the NMOS transistor will be improved.
Thereafter, referring to FIG. 3, a portion of the stressed layer 16 disposed on the PMOS transistor is removed by an etching process using a mask layer and a portion of stressed layer 16 disposed on the NMOS transistor is not removed. Then, an annealing process is performed on the portion of stressed layer 16 disposed on the NMOS transistor to provide a tensile stress, so that the tensile stress in NMOS transistor can promote mobility of electrons in a channel region of the NMOS transistor. After the annealing process, a wet etching process is performed to remove a portion of stressed layer 16 which is disposed on gate 13 of the NMOS transistor, the source/drain region 12 and the substrate 10. Specifically, the stressed layer 16 includes silicon nitride; and a solution used in the wet etching process includes hot phosphoric acid or hydrofluoric acid.
As is well known, MOS transistors formed by the conventional manufacturing method cannot withstand high voltages, and, in electrical testings, the gate oxide integrity (GOI) of the MOS transistors is poor.